1. Field of the Invention
The present invention relates to a static induction type switching device having gate regions which are buried in a semiconductor substrate and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a sectional view showing the gate structure of a conventional static induction type switching device (hereinafter referred to as "SI device") having buried gate structure such as a static induction type transistor (hereinafter referred to as "SI transistor"), a static induction type thyristor (hereinafter referred to as "SI thyristor") or the like. Referring to FIG. 1, p.sup.+ -type gate regions 5 (5a and 5b) are formed in an upper layer part of an n.sup.- -type substrate 1 by selective impurity diffusion. An n-type epitaxial layer 2 is formed on a region 1a of the n.sup.- -type substrate 1, to bury the p.sup.+ -type gate regions 5a. Thus, channel regions 8 are defined by portions of the n-type substrate 1 and the epitaxial layer 2 located between the p.sup.+ -type gate regions 5.
Gate metal electrodes 3 are formed on the p.sup.+ -type gate regions 5b. An n.sup.+ -type cathode region 4 is formed on the n type epitaxial layer 2, and a cathode metal electrode 6 is formed on the n.sup.+ -type cathode region 4. The gate metal electrodes 3 are insulated from the n-type epitaxial layer 2, the n.sup.+ -type cathode region 4 and the cathode metal electrode 6 by insulating films 7 which are formed on end portions of the n-type epitaxial layer 2 and the n.sup.+ -type cathode region 4. The p.sup.+ -type gate regions 5 are connected with each other by inpurity diffusion layers formed in a section different from that shown in FIG. 1.
FIG. 2 is a sectional view showing the gate structure of an SI device having surface gate structure. Referring to FIG. 2, p.sup.+ -type gate regions 5 are deeply formed in an upper layer part of an n.sup.- -type substrate I by selective impurity diffusion. An n.sup.+ -type cathode region 4 is also formed in the upper layer part of the n.sup.- -type substrate I between the p.sup.+ -type gate regions 5 by selective impurity diffusion, to be smaller in depth than the p.sup.+ -type gate regions 5. Thus, a channel region 8 is defined between the p.sup.+ -type gate regions 5, in a deep portion provided with no n.sup.+ -type cathode region 4.
Gate metal electrodes 3 are formed on the p.sup.+ -type gate regions 5 and a cathode metal electrode 6 is formed on the n.sup.+ -type cathode region 4 respectively, so that these electrodes 3 and 0 are insulated from each other by insulating films 7.
FIG. 3 is a sectional view showing the gate structure of an SI device having trench gate structure. Referring to FIG. 3, a large number of trenches are formed in an n.sup.- -type substrate Under these trenches, p.sup.+ -type gate regions 5 are defined by diffusing an impurity from bottom portions of the trenches. On the other hand, n.sup.+ -type cathode regions 4 are formed on upper layer parts by impurity diffusion. Thus, channel regions 8 are defined between the p.sup.+ -type gate regions 5.
Gate metal electrodes 3 are formed on the p.sup.+ -type gate regions 5 and cathode metal electrodes 6 are formed on the n.sup.+ -type cathode regions 4, so that the gate metal electrodes 3 and the cathode metal electrodes 6 are insulated from each other by insulating films 7 which are formed in stepped portions.
While the gate metal electrodes 3 shown in FIG. 3 are adapted to serve as interconnection members, such gate metal electrodes 3 may be omitted to alternatively make gate impurity diffusion layers, i.e., the p.sup.+ -type gate regions 5 themselves serve as gate interconnection members.
When reverse bias voltage is applied between the gate metal electrodes 3 and the cathode metal electrode(s) 6 in case of a normally-on type SI device having the structure shown in FIG. 1, 2 or 3, main current flowing in the channel region(s) 8 is cut off by rising potential barrier caused in the channel region(s) 8 and extracting excessive minority carriers from the gate metal electrodes 3 at the same time, whereby the SI device enters an OFF state. When zero or positive bias is applied across gates and cathodes on the other hand, the potential barrier in the channel region(s) 8 is reduced, so that the main current flows in the channel region(s) 8, whereby the SI device enters an ON state.
Characteristics relating to on/off operation of the SI device in the aforementioned manner extremely depend on the gate structure. In order to quickly extract the minority carriers for achieving high-speed turn off operation, resistance of the p.sup.+ -gate regions 5 must be reduced to the minimum.
Further, the SI device having a high breakdown voltage between the gates and the cathodes is also required, since the speed of turn-off operation and the amount of current which can be blocked depend on a breakdown voltage between the gates and the cathodes (the amount of applicable reverse bias).
On the other hand, the main current flows in the channel region(s) 8, and hence it is necessary to precisely control channel width and channel length, which are almost determined in formation of the p.sup.+ -type gate regions 5 by impurity diffusion, in order to improve on-off characteristics.
In addition to the aforementioned improvement of switching characteristics, increase in channel number is desired and refinement of the gate structure is demanded in order to reduce ON voltage.
As hereinabove described, the conventional SI devices are mainly of three types of the buried gate structure, the surface gate structure and the trench gate structure.
In the SI device of the buried gate structure shown in FIG. 1, a breakdown reverse voltage between the gates and the cathodes can be increased since the p.sup.+ -gate regions 5 are buried, and this device is advantageous for pressure-contact type packaging due to its structure.
However, it is difficult to form the n-type epitaxial layer 2 in good quality since generation of defects and autodoping from the p.sup.+ -gate regions 5 of high concentration must be suppressed in formation of the n-type epitaxial layer 2. Thus, the impurity concentration profile Of the channel region 8 is deteriorated as compared with those of the surface gate structure and the trench gate structure shown in FIGS. 2 and 3, which are formed only by the n.sup.- -type substrates 1. Further, it is difficult to accurately form the channel width and channel length of the channel region 8, due to floating of the impurity from the p.sup.+ -type gate regions 5 in formation of the n-type epitaxial layer 2, etc.
On the other hand, the SI device of the surface gate structure shown in FIG. 2 is easy to manufacture. However, it is difficult to set a breakdown reverse voltage at a high value since the p.sup.+ -type gate regions 5 are formed in the surface of the n.sup.- -type substrate I and high electric field is easily caused in p-n junction portions on the surface of the n.sup.- -type substrate 1. Thus, it is impossible to increase the amount of current which can be blocked in turn-off operation.
In the SI device of the trench gate structure shown in FIG. 3, the p.sup.+ -type gate regions 5 can be deeply formed similarly to the SI device of the buried gate structure since the same are formed by impurity diffusion from the bottom portions of the trenches, whereby the breakdown reverse voltage can be high.
In this SI device, the p.sup.+ -type gate regions 5 are formed through general ion implantation or doping with a gas containing an impurity at a high temperature after formation of the trenches. In the step of forming the p.sup.+ -gate regions 5, it is necessary to prevent diffusion of the p-type impurity toward the side surfaces of the trenches, in order to improve a breakdown reverse voltage between the gates and the cathodes. Therefore, when impurity diffusion of high concentration is performed for forming the p.sup.+ -type gate regions, it is necessary to previously largely etch the side surfaces to increase width of the trenches, thereby to prevent diffusion of the impurity toward the side surfaces of the trenches. Such countermeasure is improper for refinement. In other words, impurity concentration of the p.sup.+ -type gate regions 5 cannot be increased when refinement is desired.
Further, sufficient trench width is also required in order to prevent short-circuiting across the gate metal electrodes 3 and the cathode metal electrodes 6, and hence it is difficult to refine gate patterns and cathode patterns. In addition, the SI device of the trench gate structure is basically of surface interconnection structure, and hence it is improper to apply this SI device to a pressure contact type device, since there is the possibility that a sufficient insulation distance cannot be maintained. Although there is the one which performs no interconnection by the gate metal electrodes 3 in this structure as hereinabove described, another problem is caused in this case, such that gate resistance cannot be sufficiently reduced.